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? semiconductor components industries, llc, 2006 july, 2006 ? rev. 7 1 publication order number ncp1560/d ncp1560 full featured voltage mode pwm controller the ncp1560 pwm controller contains all the features and flexibility needed to implement voltage ? mode control in high performance single ended dc ? dc converters. this device cost effectively reduces system part count with the inclusion of a high voltage startup regulator that operates over a wide input range of 21.5 v to 150 v. the ncp1560 provides two control outputs, out1 which controls the main pwm switch and out2 with adjustable overlap delay, which can control a synchronous rectifier switch or an active clamp/reset switch. other distinctive features include: two mode over current protection, line under/overvoltage lockout, fast line feedforward, soft ? start and a maximum duty cycle limit. features ? minimum operating voltage of 21.5 v ? internal high voltage startup regulator ? dual control outputs with adjustable overlap delay ? single resistor oscillator frequency setting ? fast line feedforward ? line under/overvoltage lockout ? dual mode overcurrent protection ? programmable maximum duty cycle control ? maximum duty cycle proportional to line voltage ? programmable soft ? start ? precision 5.0 v reference ? pb ? free package is available* typical applications ? telecommunication power converters ? industrial power converters ? high voltage power modules ? +42 v automotive systems ? control driven synchronous rectifier power converters *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. tx ncp1560 + ? driver error amplifier startup feedforward uv/ov overlap delay + ? v in v out c out l out figure 1. active ? clamp forward converter out1 out2 v in ff t d drive sr opto m1 c clamp m clamp device package shipping ? ordering information ncp1560hdr2 so ? 16 2500/tape & reel ncp1560 = device code a = assembly location wl = wafer lot y = year ww = work week marking diagram 16 so ? 16 d suffix case 751b ncp1560 1 1 16 awlyww http://onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. pin connections ss dc max 1 16 v ea r t v ref c skip t d cs out2 ff gnd nc out1 uv/ov v aux v in ncp1560hdr2g so ? 16 (pb ? free) 2500/tape & reel
ncp1560 http://onsemi.com 2 v in gnd uv/ov cs ff high voltage startup regulator fault detection oscillator delay logic modulator figure 1. simplified block diagram 5.0 v reference v aux ss v ea t d r t output drivers out1 out2 uv dc max v ref cskip
ncp1560 http://onsemi.com 3 figure 2. ncp1560 functional block diagram + ? + 5.0 v reference v in gnd v ea delay logic out1 ? + ? + ? + cs s r q c ss 10 5 14 16 1 11 12 r d stop stop v in disable c cskip clock disable_ss s r q monotonic start (250 ns) disable_ss c aux dis v aux v aux out2 v aux 15 13 v aux 10 pf ff ramp (adjustable) * trimmed during manufacturing to obtain 1.3 v with r t = 101 k v in r ff ff 4 + current mirror ? + r t 2 v 10 pf i 1 + ? ? 2 v 7 oscillator ramp 2 v + ? dis dis 8 + ? 2 v max dc comparator pwm comparator + ? soft start comparator 0.5 v + ? 0.57 v + ? ss 9 one shot pulse ? + 6 cskip 2 uv/ov ? + 2 v + ? one shot pulse + ? + ? i 1 2 + ? 1.3 v* v ref t d ? 20 k 40 k v ref dc max 2 k 32 k 27 k 5.3 k 6.7 k + v dc(inv) ? r mdp r p c ff disable_v ref disable_v ref i ff disable 12.3 a + v ? ? + i v 125 k r t (600 ns) one shot pulse clock v ref v ref output latch (reset dominant) latch (reset dominant) i start v aux(on)/aux(off) 1.52 v 3.61 v 6 a
ncp1560 http://onsemi.com 4 pin description pin name application information 1 v in this pin is connected to the bulk dc input voltage supply. a constant current source supplies current from this pin to the capacitor connected on the v aux pin. the charge current is typically 13.8 ma. input voltage range is 21.5 v to 150 v. 2 uv/ov input supply voltage is scaled down and sampled by means of a resistor divider. the supply voltage must be scaled down between 1.52 v and 3.61 v within the specified input voltage range. 3 nc not connected. 4 ff an external resistor between v in and this pin adjusts the amplitude of the ff ramp in proportion to v in . by varying the feedforward ramp amplitude in proportion to the input voltage, changes in loop bandwidth are eliminated. 5 cs over current sense input. if the cs voltage exceeds 0.48 v or 0.57 v, the converter enters the cycle ? by ? cycle or cycle skip current limit mode, respectively. 6 c skip the capacitor connected between this pin and ground sets the cycle skip period. a soft ? start sequence follows at the conclusion of the fault period. 7 r t a single external resistor between this pin and gnd sets the oscillator fixed frequency. 8 dc max an external resistor between this pin and gnd sets the voltage on the max dc comparator inverting input. the duty cycle is limited by comparing the voltage on the max dc comparator inverting input to the feedforward ramp. 9 ss an internal 6.2 a current source charges the external capacitor connected to this pin. the duty cycle is limited during startup by comparing the voltage on this pin to the oscillator ramp. 10 v ea the error signal from an external error amplifier is fed into this input and compared to the feedforward ramp. a series diode and resistor offset the voltage on this pin before it is applied to the pwm comparator inverting input. 11 v ref precision 5.0 v reference output. maximum output current is 6.0 ma. 12 t d an external resistor between v ref and this pin sets the overlap delay between out1 and out2 transitions. 13 out2 output of the pwm controller with leading and trailing edge overlap delay. out2 can be used to drive a synchronous rectifier topology, an active clamp/reset switch, or both. 14 gnd control circuit ground. 15 out1 main output of the pwm controller. 16 v aux positive input supply voltage. this pin is connected to an external capacitor for energy storage. an internal current supplies current from v in to this pin. once the voltage on v aux reaches 11 v, the current source turns off. it turns on again once v aux falls to 7.0 v. during normal operation, power is supplied to the ic via this pin, by means of an auxiliary winding.
ncp1560 http://onsemi.com 5 maximum ratings symbol rating value unit v in input line voltage ? 0.3 to 150 v v aux auxiliary supply voltage ? 0.3 to 16 v i aux auxiliary supply input current 35 ma v out out1 and out2 voltage ? 0.3 to (v aux + 0.3 v) v i out out1 and out2 output current 10 ma v ref 5.0 v reference voltage ? 0.3 to 6.0 v i ref 5.0 v reference output current 6.0 ma v io all other inputs/outputs voltage ? 0.3 to v ref v i io all other inputs/outputs current 10 ma t j operating junction temperature ? 40 to 125 c t stg storage temperature range ? 55 to 150 c p d power dissipation at t a = 25 c 0.77 w r ja thermal resistance, junction ? to ? ambient 130 c/w stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: pin 1 is the hv startup of the device and is rated to the max rating of the part, or 150 v. machine model method 150 v. pins 2 ? 16: human body model 4000 v per mil ? std ? 883, method 3015. machine model method 200 v.
ncp1560 http://onsemi.com 6 electrical characteristics (v in = 48 v, v aux = 12 v, v ea = 2 v, r t = 101 k , c cskip = 6800 pf, r d = 60.4 k , r ff = 432 k , for typical values t j = 25 c, for min/max values, t j = ? 40 c to 125 c, unless otherwise noted) characteristic symbol min typ max unit startup control and v aux regulator v aux regulation startup threshold/v aux regulation peak (v aux increasing) minimum operating v aux valley voltage after turn ? on hysteresis v aux(on) v aux(off) v h 10.5 6.6 ? 11.0 7.0 4.0 11.5 7.4 ? v minimum startup voltage (pin 1) i start = 1.0 ma, v aux = v aux(on) ? 0.2 v v start(min) ? 19.3 21.5 v startup circuit output current v aux = 0 v t j = 25 c t j = ? 40 c to 125 c v aux = v aux(on) ? 0.2 v t j = 25 c t j = ? 40 c to 125 c i start 13 10 10 8 17.5 ? 13.8 ? 21 25 17 19 ma startup circuit off ? state leakage current (v in = 150 v) t j = 25 c t j = ? 40 c to 125 c i start(off) ? ? 23 ? 50 100 a startup circuit breakdown voltage (note 2) i start(off) = 50 a, t j = 25 c v (br)ds 150 ? ? v auxiliary supply current after v aux turn ? on outputs disabled v ea = 0 v v uv/ov = 0.7 v outputs enabled i aux1 i aux2 i aux3 ? ? ? 2.7 1.3 4.6 5.0 2.5 6.5 ma line under/overvoltage detector undervoltage threshold (v in increasing) v uv 1.40 1.52 1.64 v undervoltage hysteresis v uv(h) 0.080 0.098 0.120 v overvoltage threshold (v in increasing) v ov 3.47 3.61 3.75 v overvoltage hysteresis v ov(h) ? 0.145 ? v undervoltage propagation delay to output t uv ? 250 ? ns overvoltage propagation delay to output t ov ? 160 ? ns current limit cycle ? by ? cycle threshold voltage i lim1 0.44 0.48 0.52 v propagation delay to output (v ea = 2.0 v) v cs = i lim1 to 2.0 v, measured when v out reaches 0.5 v oh t ilim ? 90 150 ns cycle skip threshold voltage i lim2 0.54 0.57 0.62 v cycle skip charge current (v cskip = 0 v) i cskip 8.0 12.3 15 a 2. guaranteed by design only.
ncp1560 http://onsemi.com 7 electrical characteristics (v in = 48 v, v aux = 12 v, v ea = 2 v, r t = 101 k , c cskip = 6800 pf, r d = 60.4 k , r ff = 432 k , for typical values t j = 25 c, for min/max values, t j = ? 40 c to 125 c, unless otherwise noted) characteristic symbol min typ max unit oscillator frequency (r t = 101 k , v in = 36 v) t j = 25 c t j = ? 40 c to 125 c f osc1 285 280 300 ? 315 320 khz frequency (r t = 59 k , v in = 36 v, v ea = 1 v) t j = 25 c t j = ? 40 c to 125 c f osc2 456 444 480 ? 504 516 khz maximum duty cycle comparator maximum duty cycle (v in = 36 v, v ea = 3 v, t j = 25 c) r p = 0 , r mdp = open r p = open, r mdp = open dc max 57 75 62 80 66 85 % open circuit voltage v dcmax 0.40 0.47 0.60 v soft ? start charge current (v ss = 1.0 v) i ss(c) 5.0 6.2 7.4 a discharge current (v ss = 5.0 v, v uv/ov = 3.7 v) i ss(d) 20 52.5 ? ma pwm comparator input resistance (v 1 = 1.25 v, v 2 = 1.50 v) r in(vea) = (v 2 ? v 1 )/(i 2 ? i 1 ) r in(vea) 8.0 22 60 k lower input threshold v ea(l) 0.3 0.7 0.9 v delay to output (from v oh to 0.5 v oh ) t pwm ? 200 ? ns 5.0 v reference output voltage (i ref = 0 ma) v ref 4.9 5.0 5.1 v load regulation (i ref = 0 to 6 ma) v ref(load) ? 10 50 mv line regulation (v aux = 7.5 v to 16 v) v ref(line) ? 50 100 mv control outputs output voltage (i out = 0 ma) low state high state v ol v oh ? ? 0.25 11.8 ? ? v overlap delay (v in = 36 v) r d = 1 m leading trailing r d = 60 k leading trailing t d ? ? 50 32 342 312 77 77 ? ? 130 130 ns drive resistance (v in = 15 v) sink (v ea = 0 v, v out = 2 v) source (v ea = 3 v, v out = 10 v) r snk r src 20 50 40 90 80 170 rise time (c l = 100 pf, 10% to 90% of v oh ) t on ? 30 ? ns fall time (c l = 100 pf, 90% to 10% of v oh ) t off ? 12 ? ns
ncp1560 http://onsemi.com 8 typical characteristics figure 3. auxiliary supply voltage thresholds versus junction temperature figure 4. startup circuit output current versus junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 5 6 7 8 9 10 11 12 125 100 75 50 25 0 ? 25 ? 50 10 11 12 13 14 15 16 20 figure 5. startup circuit output current versus auxiliary supply voltage figure 6. startup circuit output current versus line voltage v aux , auxiliary supply voltage (v) v in , line voltage (v) 12 10 8 6 4 2 0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 17.5 150 125 100 75 50 25 0 0 4 8 12 16 20 figure 7. startup circuit off ? state leakage current versus line voltage figure 8. auxiliary supply current versus junction temperature v in , line voltage (v) t j , junction temperature ( c) 150 125 100 75 50 25 0 0 5 10 15 20 25 30 40 125 100 75 50 25 0 ? 25 ? 50 0 0.5 1.0 1.5 2.0 2.5 3.5 4.0 v aux , auxiliary supply voltage (v) 150 150 17 18 19 i start , startup circuit output current (ma) 17.0 i start , startup circuit output current (ma) i start , startup circuit output current (ma) 35 i start(off) , startup circuit off ? state leakage current ( a) 150 3.0 i aux , auxiliary supply current (ma) startup threshold minimum operating threshold v aux = 0 v v aux = v aux(on) ? 0.2 v t j = ? 40 c t j = 25 c t j = 125 c t j = ? 40 c t j = 25 c t j = 125 c v ea = 0 v v uv/ov = 0 v v aux = 12 v v in = 48 v v in = 48 v v aux = v aux(on) ? 0.2 v v aux = 12 v
ncp1560 http://onsemi.com 9 typical characteristics figure 9. operating auxiliary supply current versus junction temperature figure 10. line under/overvoltage thresholds versus junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 0 1 2 3 4 5 6 7 125 100 75 50 25 0 ? 25 ? 50 0 0.5 1.0 1.5 2.0 4.0 figure 11. line under/overvoltage thresholds hysteresis versus junction temperature t j , junction temperature ( c) 150 125 100 25 0 ? 25 ? 50 90 100 110 120 130 140 160 figure 12. current limit thresholds versus junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 400 425 450 475 500 525 575 600 i aux3 , operating auxiliary supply current (ma) 150 150 2.5 3.0 3.5 v uv/ov , uv/ov voltage (v) 150 v uv/ov(h) , uv/ov threshold voltage hysteresis (mv) 150 550 i lim , current limit thresholds (mv) 75 50 f osc = 440 khz uv threshold ov threshold uv hysteresis cycle skip cycle ? by ? cycle v aux = 12 v dc 50% f osc = 300 khz f osc = 87 khz ov hysteresis figure 13. current limit propagation delay versus junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 70 75 80 85 90 95 115 120 t ilim , current limit propagation delay (ns) 150 100 105 110 v aux = 12 v measured from v oh to 0.5 v oh figure 14. oscillator frequency versus junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 0 50 100 150 200 250 450 150 300 350 400 f osc , oscillator frequency (khz) r t = 390 k r t = 101 k r t = 68 k
ncp1560 http://onsemi.com 10 typical characteristics t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 3.0 3.5 4.0 4.5 5.0 5.5 6.5 7.0 150 6.0 i ss(c) , soft ? start charge current ( a) 30 35 40 45 50 55 65 70 60 charge discharge figure 15. oscillator frequency versus junction temperature figure 16. oscillator frequency versus timing resistor r t , timing resistor (k ) 400 300 250 200 150 100 50 0 100 200 300 400 600 500 f osc , oscillator frequency (khz) 350 t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 285 290 295 300 305 310 150 315 f osc , oscillator frequency (khz) r t = 101 k t j = 25 c dc 50% 525 450 225 150 75 0 0 10 20 40 60 90 dc max , maximum duty cycle (%) 375 300 30 50 t j = ? 40 c t j = 125 c 80 70 v ea = 3.0 v v dcmax = 0 v t j , junction temperature ( c) 150 125 100 75 0 ? 25 ? 50 50 60 70 80 90 100 dc max , maximum duty cycle (%) 50 25 r p = open, r mdp = open r p = 0 , r mdp = open v in = 36 v r ff = 432 k figure 17. feedforward internal resistance versus junction temperature 150 125 100 75 0 ? 25 ? 50 9 10 11 12 13 14 15 19 17 feedforward internal resistance (k ) 50 25 16 18 figure 18. maximum duty cycle versus feedforward current figure 19. maximum duty cycle versus junction temperature figure 20. soft ? start charge/discharge currents versus junction temperature i ss(d) , soft ? start discharge current (ma) t j , junction temperature ( c) i ff , feedforward current ( a)
ncp1560 http://onsemi.com 11 typical characteristics t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 4.93 4.95 4.97 4.99 5.03 t j , junction temperature ( c) r d , delay resistor (k ) 75 50 25 0 ? 25 ? 50 0 50 100 150 200 250 350 1000 800 600 400 200 0 50 100 150 t j , junction temperature ( c) 150 125 100 25 0 ? 25 ? 50 0 40 80 160 200 150 v ref , reference voltage (v) 300 t d , outputs overlap delay (ns) t d , outputs overlap delay (ns) r snk/src outputs drive resistance ( ) 150 125 100 450 50 75 120 r d = 60 k , leading leading trailing r src (v ea = 0 v, v out = 10 v) r snk (v ea = 3 v, v out = 2 v) v in = 36 v v aux = 12 v r mdp = 100 k t j = 25 c c d = 220 pf i ref = 0 ma i ref = 6 ma 5.01 t j , junction temperature ( c) 150 125 100 25 0 ? 25 ? 50 0.35 0.45 0.55 0.75 0.85 v ea(l) , pwm comparator lower input threshold (v) 50 75 0.65 figure 21. v ea input resistance versus junction temperature t j , junction temperature ( c) 150 100 50 0 ? 50 0 10 20 40 50 30 r in(vea) , v ea input resistance (k ) ? 25 125 75 25 figure 22. pwm comparator lower input threshold versus junction temperature figure 23. reference voltage versus junction temperature figure 24. outputs overlap delay versus junction temperature figure 25. outputs overlap delay versus delay resistor figure 26. outputs drive resistance voltage versus junction temperature 400 350 300 250 200 1200 1400
ncp1560 http://onsemi.com 12 typical characteristics figure 27. outputs rise time versus load capacitance c l , load capacitance (pf) 200 150 100 50 0 0 10 20 30 40 50 60 80 figure 28. outputs fall time versus load capacitance c l , load capacitance (pf) 200 150 100 50 0 0 5 10 15 20 25 35 70 t on , outputs rise time (ns) 30 t off , outputs fall time (ns) t j = ? 40 c t j = 25 c t j = 125 c t j = ? 40 c t j = 25 c t j = 125 c 175 125 75 25 175 125 75 25 measured from 10% to 90% of v oh v aux = 12 v measured from 90% to 10% of v oh v aux = 12 v detailed operating description the ncp1560 pwm controller contains all the features and flexibility needed for implementation of voltage ? mode control in high performance dc ? dc converters. this device cost effectively reduces system part count with the inclusion of a high voltage startup regulator. the ncp1560 provides two control outputs. output 1 controls the main switch of a forward or flyback topology. output 2 has an adjustable overlap delay, which can be used to control an active clamp/reset switch, a synchronous rectifier switch, or both. other distinctive features include: two mode overcurrent protection, line under/overvoltage lockout, fast line feedforward, soft ? start and a maximum duty cycle limit. the functional block diagram is shown in figure 2. the features included in the ncp1560 provide all the advantages of current ? mode control, fast line feedforward, and cycle ? by ? cycle current limit. it eliminates the disadvantages of low power jitter, slope compensation and noise susceptibility. high voltage startup regulator the ncp1560 contains an internal high voltage startup regulator that eliminates the need for external startup components. in addition, this regulator increases the efficiency of the supply as it uses no power when in the normal mode of operation, but instead uses power supplied by an auxiliary winding. the startup regulator consists of a constant current source that supplies current from the input line voltage (v in ) to the capacitor on the v aux pin (c aux ). the startup current is typically 13.8 ma. once v aux reaches 11 v, the startup regulator turns off and the outputs are enabled. when v aux reaches 7.0 v, the outputs are disabled and the startup regulator turns on. this ?7 ? 11? mode of operation is known as dynamic self supply (dss). the v aux pin can be biased externally above 7 v once the outputs are enabled to prevent the startup regulator from turning on. it is recommended to bias the v aux pin using an auxiliary supply generated out of an auxiliary winding from the power transformer. an independent voltage supply can also be used. however, if v aux is biased before the outputs are enabled or while a fault is present, the one shot pulse generator (figure 2) will not be enabled and the outputs will remain off. as the dss sources current to the v aux pin, a diode should be placed between c aux and the auxiliary supply as shown in figure 29. this will allow the ncp1560 to charge c aux while preventing the startup regulator from sourcing current into the auxiliary supply. figure 29. recommended v aux configuration i start disable c aux i supply v aux i aux to auxiliary supply v in i start power to the controller while operating in the self ? bias or dss mode is provided by c aux . therefore, c aux must be sized such that a v aux voltage greater than 7 v is maintained while the outputs are switching and the converter reaches regulation. also, the v aux discharge time (from 11 v to 7 v) must be greater that the soft ? start charge period to assure the converter turns on. the startup circuit is rated at a maximum voltage of 150 v. if the device operates in the dss mode, power dissipation should be controlled to avoid exceeding the maximum power dissipation of the controller.
ncp1560 http://onsemi.com 13 line under/overvoltage shutdown the ncp1560 incorporates a line under/overvoltage shutdown (uv/ov) circuit. the undervoltage (uv) threshold is 1.52 v and the overvoltage threshold (ov) is 3.61 v, for a ratio of 1:2.4. the uv/ov circuit can be biased using an external resistor divider from the input line. the resistor divider must be sized to enable the controller once v in is within the required operating range. if the uv or ov threshold is reached, the soft ? start capacitor is discharged, and the outputs are immediately disabled with no overlap delay as shown in figure 30. also, if an uv condition is detected, the 5.0 v reference supply is disabled. figure 30. uv/ov fault timing diagram uv or ov fault out2 out1 0 v 0 v 0 v 0 v v ov v uv uv/ov voltage v aux(off) v aux(on) v aux propagation delay to outputs (t uv or t ov )
ncp1560 http://onsemi.com 14 once the uv or ov condition is removed and v aux reaches 11 v, the controller initiates a soft ? start cycle. figure 31 shows the relationship between the uv/ov voltage, the outputs and the soft ? start voltage. the uv/ov pin can also be used to implement a remote enable/disable function. biasing the uv/ov pin below its uv threshold disables the converter. figure 31. soft ? start timing diagram (using auxiliary winding) v aux(off) v aux(on) v aux 0 v 0 v 2 v 0 v 0 v 0 v out2 out1 soft ? start voltage uv/ov voltage soft ? start feedforward ramp generator the ncp1560 incorporates line feedforward (ff) to compensate for changes in line voltage. a ff ramp proportional to v in is generated and compared to v ea . if the line voltage changes, the ff ramp slope changes accordingly. the duty cycle will be adjusted immediately instead of waiting for the line voltage change to propagate around the system and be reflected back on v ea . a resistor between v in and the ff pin (r ff ) sets the feedforward current (i ff ). the ff ramp is generated by charging an internal 10 pf capacitor (c ff ) with a constant current proportional to i ff . the ff ramp is finished (capacitor is discharged) once the oscillator ramp reaches 2.0 v. please refer to figure 2 for a functional drawing of the feedforward ramp generator. i ff is usually a few hundred a, depending on the operating frequency and the required duty cycle. if the operating frequency and maximum duty cycle are known, i ff is calculated using the equation below: i ff c ff v dc(inv) 125 k 6.7 k t on(max) where v dc(inv) is the voltage on the inverting input of the max dc comparator and t on(max) is the maximum on time. figure 18 shows the relationship between i ff and dc max . for example, if a system is designed to operate at 300 khz, with a 60% maximum duty cycle at 36 v, the dc max pin can be grounded and i ff is calculated as follows: t 1 f 1 300 khz 3.33 s t on(max) dc max t 0.6 3.33 s 2.0 s i ff c ff v dc(inv) 125 k 6.7 k t on(max) 10 pf 0.888 v 125 k 6.7 k 2.0 s 82.8 a as the minimum line voltage is 36 v, the required feedforward resistor is calculated using the equation below: r ff v in i ff 12.0 k 36 v 82.8 a 12.0 k 434 k from the above calculations it can be observed that i ff is controlled predominantly by the value of r ff , as the resistance seen into the ff pin is only 12 k . if a tight maximum duty cycle control over temperature is required, r ff should have a low thermal coefficient.
ncp1560 http://onsemi.com 15 current limit the ncp1560 has two over current protection modes, cycle ? by ? cycle and cycle skip. it allows the ncp1560 to handle momentary and hard shorts differently for the best tradeoff in performance and safety. the outputs are disabled typically 90 ns after a current limit fault is detected. the cycle ? by ? cycle mode terminates the conduction cycle (reducing the duty cycle) if the voltage on the cs pin exceeds 0.48 v. the cycle skip mode is enabled if the voltage on the cs pin reaches 0.57 v. once a cycle skip fault is detected, the outputs are disabled, the soft ? start and cycle skip capacitors are discharged, and the cycle skip period (t cskip ) commences. the cycle skip period is set by an external capacitor (c cskip ). once a cycle skip fault is detected, the cycle skip capacitor is discharged followed by a charge cycle. the charge current is 12.3 a. the cycle skip period ends when the voltage on the cycle skip capacitor reaches 2.0 v. the cycle skip capacitor is calculated using the equation below: c cskip t cskip 12.3 a 2v using the above equation, a cycle skip period of 11.0 s requires a cycle skip capacitor of 68 pf. the differences between the cycle ? by ? cycle and cycle skip modes are observed in figure 32. figure 32. over current faults timing diagram cycle skip voltage 0 v 0 v 0 v 0 v 0 v out2 out1 i lim2 i lim1 v aux(off) v aux(on) v aux cs voltage normal operation i lim2 reset i lim1 soft ? start normal operation t cskip once the cycle skip period is complete and v aux reaches 11 v, a soft ? start sequence commences. the possible minimum off time is set by c cskip . however, the actual off time is generally greater than the cycle skip period because it is the cycle skip period added to the time it takes v aux to reach 11 v. oscillator the ncp1560 oscillator frequency is set by a single external resistor connected between the r t pin and gnd. the oscillator is designed to operate up to 500 khz. the voltage on the r t pin is laser trim adjusted during manufacturing to 1.3 v for an r t of 101 k . a current set by r t generates an oscillator ramp by charging an internal 10 pf capacitor as shown in figure 2. the period ends (capacitor is discharged) once the oscillator ramp reaches 2.0 v. if r t increases, the current and the oscillator ramp slope decrease, thus reducing the frequency. if r t decreases, the opposite effect is obtained. figure 16 shows the relationship between r t and the oscillator frequency.
ncp1560 http://onsemi.com 16 maximum duty cycle a dedicated internal comparator limits the maximum on time of out1 by comparing the ff ramp to v dc(inv) . if the ff ramp voltage exceeds v dc(inv) , the output of the max dc comparator goes high. this will reset the output latch, thus turning off the outputs and limiting the duty cycle. duty cycle is defined as: dc t on t t on f therefore, the maximum on time can be set to yield the desired dc if the operating frequency is known. the maximum on time is set by adjusting the ff ramp to reach v dc(inv) in a time equal to t on(max) as shown in figure 33. the maximum on time should be set for the minimum line voltage. as line voltage increases, the slope of the ff ramp increases. this reduces the duty cycle below dc max , which is a desirable feature as the duty cycle is inversely proportional to line voltage. figure 33. maximum on time limit waveforms oscillator ramp 0 v 0 v ff ramp t t on(max) v dc(inv) 2 v an internal resistor divider from a 2.0 v reference is used to set v dc(inv) . if the dc max pin is grounded, v dc(inv) is 0.88 v. if the pin is floating, v dc(inv) is 1.19 v. this is equivalent to 60% or 80% of a 1.5 v ff ramp. v dc(inv) can be adjusted to other values by using an external resistor network on the dc max pin. for example, if the minimum line voltage is 36 v, r ff is 434 k , operating frequency is 300 khz and a maximum duty cycle of 70% is required, v dc(inv) is calculated as follows: v dc(inv) i ff 6.7 k t on(max) c ff 125 k v dc(inv) 88.2 a 6.7 k 2.33 s 10 pf 125 k 1.10 v this can be achieved by connecting a 45.3 k resistor from the dc max pin to gnd. the maximum duty cycle limit can be disabled connecting a 100 k resistor between the dc max and v ref pins. 5.0 v reference the ncp1560 includes a precision 5.0 v reference output. the reference output is biased directly from v aux and it can supply up to 6 ma. load regulation is 50 mv and line regulation is 100 mv within the specified operating range. it is recommended to bypass the reference output with a 0.1 f ceramic capacitor. the reference output is disabled when an uv fault is present. pwm comparator the output of an external error amplifier is compared to the ff ramp by means of the pwm comparator. the external error amplifier drives the v ea input. there is a 0.7 v offset between the v ea input and the pwm comparator inverting input. the offset is provided by a series diode and resistor. if the voltage on the v ea input is below 0.7 v, the outputs are disabled. the pwm comparator controls the duty cycle by turning off the outputs once the ff ramp voltage exceeds the offset v ea voltage. the v ea range required to control the dc from 0% to dc max is given by the equation below: v ea(l) v ea i ff dc 186.56 pf f v ea(l) where, v ea(l) is the pwm comparator lower input threshold. soft ? start soft ? start (ss) allows the converter to gradually reach steady state operation, thus reducing startup stress and surges on the system. the duty cycle is limited during a soft ? start sequence by comparing the oscillator ramp to the ss voltage (v ss ) by means of the soft ? start comparator. a 6.2 a current source starts to charge the capacitor on the ss pin once faults are removed and v aux reaches 11 v. the soft ? start comparator controls the duty cycle while the ss voltage is below 2.0 v. once v ss reaches 2.0 v, it exceeds the oscillator ramp voltage and the soft ? start comparator does not limit the duty cycle. figure 34 shows the relationship between the outputs duty cycle and the soft ? start voltage. figure 34. soft ? start timing diagram out1 out2 v ss oscillator ramp
ncp1560 http://onsemi.com 17 if the soft ? start period is too long, v aux may discharge to 7.0 v before the converter output is completely in regulation causing the outputs to be disabled. if the converter output is not completely discharged when the outputs are reenabled, the converter will eventually reach regulation exhibiting a nonmonotonic startup behavior. but, if the converter output is completely discharged when the outputs are reenabled, the cycle may repeat and the converter will not start. in the event of an uv, ov, or cycle skip fault, the soft ? start capacitor is discharged. once the fault is removed, a soft ? start cycle commences. the soft ? start steady state voltage is approximately 4.1 v. control outputs the ncp1560 has two in ? phase control outputs, out1 and out2, with adjustable overlap delay (t d ). out2 precedes out1 during a low to high transition and out1 precedes out2 at any high to low transition. figure 35 shows the relationship between out1 and out2. figure 35. control outputs timing diagram t d (trailing) t d (leading) out1 out2 generally, out1 controls the main switching element. output 2, once inverted, can control a synchronous rectifier. the overlap delay prevents simultaneous conduction. output 2 can also be used to control an active clamp reset. once v aux reaches 11 v, the internal startup circuit is disabled and the one shot pulse generator is enabled. if no faults are present, the outputs turn on. otherwise, the outputs remain off until the fault is removed and v aux reaches 11 v again. the control outputs are biased from v aux . the outputs can supply up to 10 ma each and their high state voltage is usually 0.2 v below v aux . therefore, the auxiliary supply voltage should not exceed the maximum input voltage of the driver stage. if the control outputs need to drive a lar ge capacitive load, a driver should be used between the ncp1560 and the load. on semiconductor?s mc33152 is a good selection for an integrated driver. figures 27 and 28 shows the relationship between the output?s rise and fall times vs capacitive load. time delay the overlap delay between the outputs is set connecting a resistor (r d ) between the t d and v ref pins. an overlap delay of 80 ns is obtained when r d is 60 k . a higher delay is obtained by increasing r d . as r d increases, the bias current of the time delay circuit is reduced, increasing its noise susceptibility. if a delay higher than 150 ns is required, it is recommended to place a small capacitor between the t d pin and ground. the output duty cycle can be adjusted from 0% to 85% selecting appropriate values of r ff and v dc(inv) . it should be noted that the overlap delay may cause out2 to reach 100% duty cycle. therefore, if out2 is used, the maximum duty cycle of out2 needs to be kept below 100%. the maximum overlap delay, t d(max) , depends on the maximum duty cycle and frequency of operation. the maximum overlap delay is calculated using the equation below. t d(max)
(1 dc) 2 ? for example, if the converter operates at a frequency of 300 khz with a maximum duty cycle of 80%, the maximum allowed overlap delay is 333 ns. however, this is a theoretical limit and variations over the complete operating range should be considered when selecting the overlap delay. additional information a 100 w dc ? dc converter for telecom systems is designed and implemented using the ncp1560. the converter delivers 100 w at 3.3 v and achieves a full load efficiency of 85%. the system is built using a 4 layer fr4, single sided board. the components location within the board is shown in figure 36 and the complete circuit schematic is shown in figure 37. the converter design is discussed in application note and8105/d. please contact your sales representative for board availability.
ncp1560 http://onsemi.com 18 figure 36. board arrangement 3.10? 2.70?
ncp1560 http://onsemi.com 19 ? + ? + n/c uv/ov cskip gnd 4 5 15 13 10 8 9 7 c28 1000 p c8 0.1 c7 10 r5 c5 0.1 c6 0.01 r4 47.5 k on/off e3 r7 110 k c9 2200 p r8 0 (short) 1 3 2 16 11 12 6 14 rt ss out2 out1 cs v in v aux v ref t d c1 4.7 c2 4.7 c3 4.7 c4 4.7 c27 0.1 l1 10 h e1 v in e2 r1 1 m r2 100 r3 487 k c11 1000 p r10 100 r11 6.81 v aux mmbd914 d2 c10 0.1 d6* murs120t3 d1 mmbd914 r12 10 k xt1 1:100 c22 1000 p r27 6.2 r25 10 k ntb75n03 l09 x4 r23 0 (short) x3 ntb75n03l09 1000 p c21 r26 6.2 r24 10 k c20 330 c19 330 c18 47 c17 47 c16 47 c15 47 l2 2 h 0 (short) d7 mmbd914 x5 mmbt2907 ntb30n20 x1 r16 10 k c12 0.1 0 (short) r15 c14 0.1 r18 5.1 k c23 0.1 mmbd914 d5 xt3 ff v ea 8 7 6 5 1 2 3 4 n/c in_a gnd in_b n/c out_a out_b v cc u2 mc33152 3.3 v e5 e4 10 r31 100 p c29 sec_pwr r30 10 k r19 10 k u6b lm358 1000 p c30 u3 tlv431 0.1 c31 7 d9 mmbd914 r29 5.1 k 110 k 150 k r22 3 4 5 c25 0.1 c24 470 p r20 2 k r6 1 k r21 249 k 65 1 23 48 u4 sfh6156a ? 4 figure 37. complete circuit schematic u6a lm358 sec_pwr 1t 6,7 8,9 5t 3t 2t 45 10 2 111 u1 ncp1560 + ? + ? v aux v aux dc max c26* 0.1 x2 irfr9220 r17 10k c13 0.047 d4 mmbd914 v ref v ref *note: d6 is removed for active clamp/reset operation. c26 is removed for reset winding operation. xt2 ea (out) r28 out2 (isolated) out2 (isolated) x6 mjd44h11 r14 1.27 k r13 49.9 d10 1pmt5929bt1 d8 mmbt914 r9 0 ea (out) r33 0 r34 open d3 open a b b a
ncp1560 http://onsemi.com 20 package dimensions so ? 16 d suffix case 751b ? 05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp1560/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative the product described herein (ncp1560) may be covered by one or more u.s. patents. there may be other patents pending.

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